//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2008-2012 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
// Version and Release Control Information:
//
// File Revision       : 127275
// File Date           :  2012-03-19 15:37:15 +0000 (Mon, 19 Mar 2012)
// Release Information : PL401-r0p1-00eac0
//------------------------------------------------------------------------------
// Purpose : This is a mux tree
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//
//        *** AUTOMATICALLY GENERATED, ONLY MODIFY MARKED SECTIONS ***
//
//  Config :
//           o  FIFO width  = 6
//
//
//------------------------------------------------------------------------------


module nic400_ib_chiplink_slv_axi4_tpv_ib_b_fifo_wr_mux2_ysyx_rv32
(
  // Inputs
  din_0,
  din_1,
  sel,

  // Outputs
  dout
);

//-----------------------------------------------------------------------------
// Port Declarations
//-----------------------------------------------------------------------------
  input  [5:0]    din_0;
  input  [5:0]    din_1;
  input           sel;

  output [5:0]    dout;

//-----------------------------------------------------------------------------
// Main Code
//-----------------------------------------------------------------------------
nic400_cdc_comb_mux2_ysyx_rv32 u_cdc_mux_0
  (
    .din1_async (din_0[0]),
    .din2_async (din_1[0]),
    .sel        (sel),
    .dout_async (dout[0])
  );
nic400_cdc_comb_mux2_ysyx_rv32 u_cdc_mux_1
  (
    .din1_async (din_0[1]),
    .din2_async (din_1[1]),
    .sel        (sel),
    .dout_async (dout[1])
  );
nic400_cdc_comb_mux2_ysyx_rv32 u_cdc_mux_2
  (
    .din1_async (din_0[2]),
    .din2_async (din_1[2]),
    .sel        (sel),
    .dout_async (dout[2])
  );
nic400_cdc_comb_mux2_ysyx_rv32 u_cdc_mux_3
  (
    .din1_async (din_0[3]),
    .din2_async (din_1[3]),
    .sel        (sel),
    .dout_async (dout[3])
  );
nic400_cdc_comb_mux2_ysyx_rv32 u_cdc_mux_4
  (
    .din1_async (din_0[4]),
    .din2_async (din_1[4]),
    .sel        (sel),
    .dout_async (dout[4])
  );
nic400_cdc_comb_mux2_ysyx_rv32 u_cdc_mux_5
  (
    .din1_async (din_0[5]),
    .din2_async (din_1[5]),
    .sel        (sel),
    .dout_async (dout[5])
  );


endmodule

// --================================= End ===================================--
